1. Field of the Invention
The invention generally relates to a method for manufacturing a semiconductor device, and more specifically, to a method for manufacturing a semiconductor device that does not require the manufacture of a dummy pattern to form an isolated pattern on a device, and improves resolution and process margins to obtain a highly-integrated transistor.
2. Brief Description of Related Technology
Semiconductor device pattern size is reduced as the devices become more highly integrated. In order to form a fine pattern, Various equipment and processes have been designed to form fine patterns for these devices. For example, a fine pattern may be obtainable by reducing an exposure wavelength, or by enlarging the size of a lens. However, these methods require new equipment development and increased manufacturing cost, which, in turn, results in difficulties in managing the equipment.
In an alternative method that uses conventional equipment employs a double exposure technology and a spacer patterning technology (SPT). FIGS. 1 and 2 are plane diagrams illustrating a conventional method for manufacturing a semiconductor device using SPT. FIG. 1 shows an isolated pattern 110 formed in a peripheral circuit region of a substrate 100. The isolated pattern 110 includes a line-type pattern 110a and a rectangular pad 110b formed on the line-type pattern 119a. A general photolithography process can be used to form patterns shown in FIG. 1. Photolithography methods, however, are limited by increased integration of the device. To overcome the limits, there are efforts to apply a light source having a short wavelength, an illuminator having high numerical aperture, and various resolution enhancement technology (RET) processes. The illuminator or the RET improves a margin of the photolithography process in dense patterns or half-dense patterns. However, the isolated pattern may reduce a margin in depth of focus (DOF).
In an etching process after the photolithography process for the isolated pattern of FIG. 1, a relatively larger bias is applied to the isolated pattern than to the dense pattern, which bias requires a smaller critical dimension in the etching process than in the photolithography process. During the photolithography process, a focus and an exposure latitude (EL) margin are reduced. To prevent the reduction, a method of forming a dummy pattern between an isolated pattern and its adjacent isolated pattern has been suggested.
FIG. 2 illustrates formation of a dummy pattern between isolated patterns. As shown, an isolated pattern 210 is formed over a semiconductor substrate 200, and a dummy pattern 220 is formed between the isolated patterns 210.
Although a method of forming a dummy pattern between isolated patterns has been suggested to increase a process margin and resolution of transistors in semiconductor device manufacturing methods, the process margin and resolution that can be increased by the dummy pattern are limited.